The present invention relates to a semiconductor memory device and a corresponding method of manufacture.
S. K. Lahiri: MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMs: A New Concept, Physics of Semiconductor Devices, V. Kumar and S. K. Agarwal (eds.), Narosa Publishing House, New Dehli, India, 1998, pages 951-956, the basic idea of charge coupled device (CCD) electrically erasable programmable read-only memory (EEPROMS) is known. Particularly, this conference paper discloses the general idea to arrange EEPROM gate structures each having a floating and a control (CCD) gate above a substrate in rows separated by rails of active areas or injectors provided in the substrate. However, S. K. Lahiri fails to disclose a suitable memory address scheme for such a CCD EEPROM taking into consideration a dynamic clocking. Moreover, this document also fails to disclose appropriate cell layouts and operation modes.
For example, CCD devices are known from W. S. Boyle, G. E. Smith: Charge Coupled Semiconductor Devices. The Bell System Technical Journal. American Telephone and Telegraph Company: New York, Apr. 1970. Pages 587-593; Rudolf Mxc3xcller: Bauelemente der Halbleiter-Elektronik. Springer Verlag: Berlin, Heidelberg, New York, London, Paris, Tokyo 1987. Pages 192-195; Kurt Hoffmann: VLSI-Entwurf. Modelle und Schaltungen. Oldenbourg Verlag: Mxc3xcnchen, Wien 1996. Pages 296-297; and Lev I. Berger: Semiconductor Materials. CRC-Press: 1997. Page 445.
EEPROM devices are generally well known in the state of the art. EEPROM cells are used to store information, which is accessible after switching the power supply off and on again, while being able to modify the stored information multiple times by pure electrical means. EEPROM cells usually have source and drain contacts forming a MOS transistor. Information is read out by measuring the attributes of the output characteristic, which is dependent of the information stored in a gate structure having floating and control gate.
The overall transfer characteristic (programming conditions to read current) is highly nonlinear and strong dependent on several side effects and production fluctuations, i.e., the Fowler-Nordheim tunneling current is more than exponentially dependent on the electric field across the oxide. So the programming voltage and the oxide thickness have severe influence on the programming process. Thus, these parameters must be adjusted with high precision. These accuracy problems limit the multilevel ability of known cell concepts to 2 bits per cell.
Fast cells are critical and must be handled with complex algorithms. Usually, only cells of a single word line can be programmed at the same time. During sensing, there is a static current consumption through S and D of the MOS transistor. During parallel programming of cells in the test phase, there is a static current due to the gate induced drain leakage, which must be supplied by a charge pump. This current driving pump is area consuming.
Using drain and source contacts, the cell area of typical cells in embedded EEPROM modules results in 22*F2 to 70*F2. The world record for cells with drain and source contacts is 8.8*F2.
Nowadays new applications for non-volatile memories are borne, one of that is the possibility to store photos or music in solid state device. In this kind of application is required a sequential data access to the memory.
Therefore, it is an object of the present invention to provide an improved semiconductor memory device and a corresponding manufacturing method.
The idea underlying the present invention is to combine the charge shifting, receiving or providing (from now on denoted only by shifting) ability and the possibility to store charge non-volatile in an oxide or on a floating gate (EEPROM) or a similar structure. The device or memory cells according to the invention will therefore be called charge coupled EEPROM cells or CC-EEPROM cells herein below.
In fact, by combining CCD and EEPROM technologies, it is possible to increase the density of the memory andxe2x80x94at the same timexe2x80x94to build a non-volatile memory that is sequentially addressable itself and even usable as a volatile memory.
CCD technique is known to operate with 8-bit resolution. In combination with the linear transfer characteristic of the charge coupled EEPROM and the self limiting programming, this provides deep multilevel ability. Fast cells do not have any influence on the programming process, because the programming stops, when all charge carriers tunneled to the floating gate. It is possible, to shift charge carriers into the cell area and to program a huge number of word lines in parallel. This cuts the programming time of some order of magnitude. There is no static current consumption during read. Minimum size cells (4F2) are possible, because the cell does not have drain or source contacts. Reduction of logic in the bit line and word line section result in less chip area. There is an additional volatile memory functionality (i.e., using the same technology, it is also possible to implement high density memory buffer).
Preferred embodiments are listed in the respective dependent claims.
According to a preferred embodiment, the gate structures include a stack of a tunnel oxide, a floating gate, and an isolation structure.
According to another preferred embodiment, the active regions are arranged at different ends of neighboring strips.
According to another preferred embodiment, the active regions are electrically connectable to the gate structures of the corresponding strip using a respective control gate structure.
According to another preferred embodiment, the respective control gate structure runs in parallel with the respective outermost gate structures at the corresponding end.
According to another preferred embodiment, every third of the word lines is connected to a common wiring line.
According to another preferred embodiment, the second and first directions are perpendicular to each other.
According to another preferred embodiment, the doping concentration of the substrate is varied in a surface region of the strip regions.
According to another preferred embodiment, a region of the second conductivity type is buried in the substrate along the strip regions.
According to another preferred embodiment, the gate structures, the word lines and the trenches have minimum design width F forming a cell dimension of 4F2.
According to another preferred embodiment, there are the method of providing the trenches by means of an etching process using a hard mask, providing an oxide layer on the inner surface of the trenches; depositing a layer of isolation material on the resulting structure; planarizing the layer of isolation material by a chemical-mechanical polishing process such that it levels with the hard mask.
According to another preferred embodiment, there are the steps of removing the hard mask, providing a tunnel oxide layer and a first polysilicon layer over the resulting structure, and planarizing the first polysilicon layer by a chemical-mechanical polishing process such that it levels with the isolation material for forming a floating gate region.
According to another preferred embodiment, there are the steps of providing a third polysilicon layer over the resulting structure, and patterning the third polysilicon layer for forming an extension of the floating gate region.
According to another preferred embodiment, there are the steps of providing an isolation layer having contact holes between the first and third polysilicon layer, the contact holes being arranged for providing an electrical connection between the first and third polysilicon layer. This has the advantage that in the patterning step of the third polysilicon layer the isolation layer may act as etching stop preventing damage of the first polysilicon layer, if there is a mask misalignment.
According to another preferred embodiment, there are the steps of removing the hard mask, providing a tunnel oxide layer and a first polysilicon layer over the resulting structure, and patterning the first polysilicon layer for forming a floating gate region which partly overlaps the isolation material in the trenches.
According to another preferred embodiment, there are the steps of providing an isolation layer and a second polysilicon layer for forming a control gate region over the resulting structure; and forming the plurality of gate structures by patterning the tunnel oxide layer, first polysilicon layer, isolation layer and second polysilicon layer.
According to another preferred embodiment, there is at least one of the steps of enhancing the doping concentration of the substrate in a surface region of the strip regions using a first implantation process and burying a region of the second conductivity type in the substrate along the strip regions using a second implantation process.
Embodiments of the present invention are illustrated in the accompanying drawings and described in detail in the following.